Technology Description:
Resulting from the CAMES project, Accord’s 15-FPGA Secure Accelerator is a high performance, compact, reliable, sustainable, and affordable alternative to networks of unsuitable, expensive and large-footprinted cluster blades. The compact, adaptive Field Programmable Gate Array (FPGA) hardware is supported by a development suite that includes MNB Technologies' mathBus logic module control interface and fastLib mathematical logic module libraries, creating a tightly-integrated, programmable solution to model execution for decision support systems. Security and software protection is provided by Accord’s reconfigurable architecture for software protection (RASP).
The CAMES effort also resulted in a technical approach and architecture for creation of a high performance service-oriented architecture (SOA) for modeling - necessary to improve the results of military modeling operations. The CASS/GRAB Multistatic application, used to model the ocean environment to determine optimal positioning of assets to maximize sonar performance, provided the case study for designing the CAMES architecture.
The resulting approach found it necessary to return to the math underlying the original model. The approach is to specify and build a reconfigurable (FPGA) solution based on standard math library modules. These modules are then organized into a Service-Oriented Architecture (SOA) to achieve acceleration gains. This task required a hardware architecture having the requisite computational density to minimize SOA communication overhead.
The resulting Secure Accelerator architecture’s specification includes Eigenvalue computation and computational object management that can be fully pipelined. Underlying modules are validated using test suites based on each buildup of the pipeline. The hardware platform uses existing single FPGA boards, interconnected via a shared memory.
Because of the high computational density provided by FPGA acceleration, a high performance SOA can be implemented to provide accelerated modeling services across platforms of widely varying sizes.
There are clear advantages to using hardware acceleration techniques when trying to achieve high performance computing (HPC) throughput levels with an SOA. The structural and sustainability advantages of an SOA can be leveraged using service nodes operating at ultra-high processing speeds. This approach reduces inter-cluster processor communications, and achieves the goal of encapsulated distributed objects.
Nodes in this architectural design provide reconfigurable acceleration using proven FPGA 30 GFLOP execution engines. Fifteen accelerator units can be packed into a 4U (7.5 inch) chassis. The system then uses conventional cluster Gigabit Ethernet or fiber optic interprocessor communications in a shared memory symmetric multiprocessor.
Using Accord’s RASP technology, the unit can be converted into a secure processing facility where software is protected from reverse engineering, and results can be distributed over multi-level security channels.
Benefits:
The chief benefits of Accord’s SOA architecture and library development technology defined as a result of the CAMES project are:
- The architecture is a reconfigurable execution accelerator and library development tool and integration method for a Service Oriented Architecture
- It has significant footprint savings – could be a factor of 25 to 50 smaller in physical dimensions and weight, offering a factor of 25 less heat generated with corresponding power consumed
- CAMES enables acceleration computation on small platforms
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